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In this paper we introduce control flow prediction (CFP) in parallel register sharing architecture. The main idea behind this concept is to use a step beyond the prediction of common branch and permitting the hardware to have the information about the CFG (Control Flow Graph) components of the program to have better branch decision in navigation. The degree of ILP depends upon the navigation bandwidth of prediction mechanism. It can be increased on increase of control flow prediction. By this the size of initiation is increased that permit the overlapped execution of multiple independent flow of control. It can allow multiple branch instruction that can be resolved simultaneously. These are intermediate steps to be taken in order to increase the size of dynamic window can achieve a high degree of ILP exploitation.