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A smart temperature sensor in 0.7 m CMOS is ac-curate to within 0.1 C (3) over the full military temperature rangeof 55 Cto125 C. ThesensorusessubstratePNPtransistors to measure temperature. Errors resulting from nonidealities in the readout circuitry are reduced to the 0.01 C level. This is achieved by using dynamic element matching, a chopped currentgain independent PTAT bias circuit, and a low-offset second-order sigma-delta ADC that combines chopping and correlated double sampling. Spread of the base-emitter voltage characteristics of the substrate PNP transistors is compensated by trimming, based on a calibration at one temperature. A high trimming resolution is obtained by using a sigma-delta current DAC to fine-tune the bias current of the bipolar transistors.