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An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (GPUs),(b) two or more associated memory banks (logically or physically partitioned),(c) a specialized controller, and (d) a local bus providing signal coupling compatible with the PCI industry standards. The controller handles most of the primitive operations to set up and control GPU computation. Thus, the computer's central processing unit (CPU) can be dedicated to other tasks. In this case a few controls (simulation start and stop signals from the CPU and the simulation completion signal back to CPU), GPU programs and input/output data are exchanged between CPU and the expansion card. Moreover, since on every time step of the simulation the results from the previous time step are used but not changed, the results are preferably trans ferred back to CPU in parallel …