作者
Sang Yoon Park, Pramod Kumar Meher
发表日期
2013/5/19
研讨会论文
2013 IEEE International Symposium on Circuits and Systems (ISCAS)
页码范围
1376-1379
出版商
IEEE
简介
In this paper, we present high throughput and power-efficient architectures for the implementation of integer DCT of different lengths to be used in upcoming High Efficiency Video Coding (HEVC). We have shown that efficient matrix-multiplication schemes could be used to derive parallel architectures for 1-D integer DCT of different lengths. Apart from that we have proposed three different flexible architectures which could be used for implementing the DCT of any of the prescribed lengths such as 4, 8, 16 and 32, each having particular advantage in terms of area, delay, or power. The proposed architectures can provide higher throughput at a lower operating frequency than the existing architectures for HEVC. Furthermore, it can support Ultra-High-Definition (UHD) 7680×4320 @30fps video which is one of the applications of HEVC.
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SY Park, PK Meher - 2013 IEEE International Symposium on Circuits and …, 2013