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The architecture and the implementation of a 2K/4K/8K-point complex fast Fourier transform (FFT) processor for an OFDM system are presented. The processor can perform 8K-point FFT every 273 /spl mu/s, and 2K-point every 68.26 /spl mu/s at 30 MHz which is enough for the OFDM symbol rate. The architecture is based on the Cooley-Tukey (1965) algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition and shuffle memories are used for the implementation of multi-dimensional transforms. The CORDIC processor is employed for the twiddle factor multiplications in each dimension. A new twiddle factor generation method is also proposed for saving the size of ROM required for storing the twiddle factors.