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The present invention is directed to a floating gate MOSFET memory device and to such a device fabri cated with and coupled to a fast bipolar transistor for forming an EEPROM cell or a programmable logic device. The combined bipolar/MOS technology allows the memory device to be read at bipolar speeds while also allowing MOSFET reprogrammability. Unlike conventional floating gate memory MOSFETS which require at least two layers of polysilicon separated by an interpoly oxide, the MOSFETS fabricated according to the present invention require only a single layer of polysilicon deposited in a two-step process. Thus, both the bipolar and MOS devices may be fabricated using a single polysilicon layer process which provides high yields. Additionally, despite the inclusion of an MOS device, the fabrication process according to the present