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The on chip communication intention is difficult due to communication necessities and the difficulty of the objective application is great. Notably, different communication areas might be actualized utilizing a similar chip range, for example, to enable various parallel applications to be stacked onto the device. So the system on chip (SoC) deployed in different topologies with different design parameters to achieve the requirements of the target application. Classical communication methods such as point to point, the bus is not an appropriate solution for future SoCs. That is difficult to send signals starting with one end then onto the next term of a clock cycle. Issues, for example, global wire delay and global synchronization will restrict us. With a specific end goal to beat these problems, architect utilizes new models, procedures, and tools from network design field and apply them to SoCs plan that prompts modern …