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To achieve energy optimal computing, processor resources must be adjusted dynamically to the computing needs of a program. The computational needs of an application may change during its execution depending on the type and locality of the processed data. It has been previously suggested that while a processor waits for data on a cache miss, dynamic voltage and frequency scaling (DVFS) may be used to reduce the energy consumption. However, due to the overheads involved in DVFS such as capacitor charging/discharging time and PLL locking time, fine-grain DVFS did not gain attraction. In this paper, we present a fine-grain DVFS scheme based on the prediction of program execution behavior. If a program is predicted to stay in a low IPC mode for a long period, it may be worthwhile to tolerate the PLL lock time overhead for achieving potential energy savings. The run-time prediction scheme is based on …