发明者
Claude Basso, Jean Calvignac, Natarajan Vaidhyanathan, Fabrice Verplanken
发表日期
2006/12/7
专利局
US
专利申请号
11142937
简介
0009. According to a first aspect of the present invention, a method of Summing at least three integer addends using a SIMD processor includes the steps of generating a vector Sum of the at least three addends, generating a vector carry indicative of overflows resulting from the generation of the vector Sum of the at least three addends, and using the vector Sum and the vector carry to calculate the sum of the at least three addends.
学术搜索中的文章
C Basso, J Calvignac, N Vaidhyanathan, F Verplanken - US Patent App. 11/142,937, 2006