发明者
Jean Louis Calvignac, Marco Heddes, Joseph Franklin Logan
发表日期
2006/12/12
专利局
US
专利号
7149212
专利申请号
10095844
简介
An interface to interconnect Network Processor and Sched uler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue. re quest, FlowEnqueue. response, PortEndueue. request and PortStatus. request.
学术搜索中的文章
JL Calvignac, M Heddes, JF Logan - US Patent 7,149,212, 2006