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Reducing power dissipation of any device at design stage leads to saving of power consumption in the lifetime of the device that eventually results in saving of energy and resources. With the emergence of Green Computing, energy efficiency has become an important criterion in designing any device. In this work, we are going to design an LVTTL and SSTL IO Standards based energy efficient FSM on a 16nm Ultrascale Plus FPGA. Manufacturer of Ultrascale Plus FPGA claims that it consumes half power in comparison to 7 Series (28nm) FPGA. Here, the power consumption of design of FSM for two different IO standards, LVTTL and SSTL is observed at different output loads: 0,100 and 10000. We compare the power consumptions of the design for LVTTL and SSTL IO standards to find the most energy efficient architecture for our design among the two. At output load 0, there is 36.51% saving in total on chip power …