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We present a robust, all-digital True Random Number Generator (TRNG) architecture that efficiently combines low-quality physical random number generators (PRNGs) with integrated de-correlation and de-biasing. A 65-nm CMOS TRNG test chip demonstrates NIST test-suite compliance across 0.5-1.0 V supply voltage and −20-100 °C, even with significant PRNG entropy degradation. The measured 2.58 pJ/bit is the lowest among all-digital NIST-compliant TRNGs. In terms of energy, area and performance metrics, this digital implementation is especially suited for advanced CMOS process nodes.