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: Researchers in computer systems and micro-architecture have advocated for the integration of hardware data compression units into microprocessors' memory hierarchies to enhance performance, energy efficiency, and functionality. Nevertheless, prior research, particularly in cache compression, has often relied on unverified assumptions regarding the performance, power consumption, and area overheads of proposed compression algorithms and hardware implementations. In this study, a novel lossless compression algorithm tailored for rapid online data compression, specifically targeting cache compression, is introduced. This algorithm incorporates innovative features, such as the consolidation of compressed lines into single cache lines and the ability to compress multiple words in parallel using a single dictionary, all without compromising compression ratio. Additionally, the proposed algorithm is translated into a register transfer level hardware design, allowing for the estimation of performance, power consumption, and area requirements