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III-V solar cell cost reduction and direct III-V/Si integration can both be realized by depositing a thin layer of high-quality Ge on relatively low-cost Si substrates. However, direct epitaxial growth of Ge on Si substrates is difficult due to the 4% lattice mismatch between the film and the substrate. Threading dislocations (TDs) introduced within the Ge layer have a detrimental effect on device performances. The goal of this research is to address the perennial need to minimize the defect density of Ge epilayers grown on a Si substrate. We seek to accommodate the effects of the lattice mismatch by introducing a porous Si interface layer to intercept dislocations and prevent them from reaching the active layers of the device. The porous Si layer is formed through dislocation-selective electrochemical deep etching and thermal annealing. The porous layer created beneath the top Ge layer can both act as dislocation traps and …