发明者
Shivam Priyadarshi, Brandon Harley Anthony Dwiel, Rami Mohammad A Al Sheikh, Harold Wade Cain III
发表日期
2019/3/5
专利局
US
专利号
10223278
专利申请号
15273270
简介
Systems and methods are directed to selectively bypassing allocation of cache lines in a cache. A bypass predictor table is provided with reuse counters to track reuse characteristics of cache lines, based on memory regions to which the cache lines belong in memory. A contender reuse counter provides an indication of a likelihood of reuse of a contender cache line in the cache pursuant to a miss in the cache for the contender cache line, and a victim reuse counter provides an indication of a likelihood of reuse for a victim cache line that will be evicted if the contender cache line is allocated in the cache. A decision whether to allocate the contender cache line in the cache or bypass allocation of the contender cache line in the cache is based on the contender reuse counter value and the victim reuse counter value.
引用总数
2020202120222023202412241
学术搜索中的文章
S Priyadarshi, BHA Dwiel, RMA Al Sheikh, HW Cain III - US Patent 10,223,278, 2019