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This paper presents a new quasi adiabatic logic family that uses a pair of complementary split-level sinusoidal power supply clocks for digital low power applications such as sensors. The proposed two phase clocked adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. By removing the diode at the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. We design and simulate NOT, NAND, NOR and Exclusive-OR logic gates based on 2PASCL with SPICE implemented using 0.18—m CMOS technology. A driving pulse with the height equal to Vdd is supplied to the gates. From the simulation results, 2PASCL inverter logic can save up to 97% of energy dissipation compared with static CMOS logic at transition frequencies of 10 to 100 MHz. It also shows the lowest in energy dissipation compared with other proposed simple adiabatic logic inverters.