作者
K Akarvardar, D Elata, R Parsa, GC Wan, K Yoo, J Provine, P Peumans, RT Howe, H-SP Wong
发表日期
2007/12/10
研讨会论文
2007 IEEE International Electron Devices Meeting
页码范围
299-302
出版商
IEEE
简介
The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at V DD = 1.5 V while occupying an area as small as 0.03 mum 2 .
引用总数
20082009201020112012201320142015201620172018201920202021202220234721241621152116134811713
学术搜索中的文章
K Akarvardar, D Elata, R Parsa, GC Wan, K Yoo… - 2007 IEEE International Electron Devices Meeting, 2007