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The paper presents a medium power amplifier (PA) design for 2.4 GHz applications in pure 0.13 /spl mu/m CMOS technology. The design has been done with reliability concern and presents high current layout considerations. It consists of evaluating the maximum current in the access lines and sizing the devices as well, without degrading the overall performance. The front end is composed of two stages using several transistors in cascade configuration. It can deliver at least 20 dBm at the maximum output power with a measured compression point better than 16 dBm. The chip has been integrated in 0.13 /spl mu/m 1.2 V and 2.5 V STMicroelectronics CMOS technology. The power stage consumes 220 mA under 2.5 V.