作者
Veerle Derudder, Bruno Bougard, Aissa Couvreur, Andy Dewilde, Steven Dupont, L Folens, Lieven Hollevoet, Frederik Naessens, David Novo, Praveen Raghavan, Thomas Schuster, Kurt Stinkens, J-W Weijers, Liesbet Van der Perre
发表日期
2009/6/16
研讨会论文
2009 Symposium on VLSI Circuits
页码范围
292-293
出版商
IEEE
简介
This paper describes the implementation of an energy-efficient digital SDR baseband platform. The multi processor system-on-chip (MPSOC) is implemented in 90nm CMOS technology and occupies 32mm2. It incorporates all digital signal processing required by the physical layer of the WiFi(802.11n), WiMax(802.16e), mobile TV and 3GPP-LTE standards. The heterogeneous architecture with hierarchical wake-up achieves 5mW idle time power, is capable of delivering a net data rate in excess of 200Mbps and consumes 231mW during 108Mbps WLAN 2×2 MIMO Rx, achieving 2.14nJ/b energy efficiency.
学术搜索中的文章
V Derudder, B Bougard, A Couvreur, A Dewilde… - 2009 Symposium on VLSI Circuits, 2009