作者
Bruno Bougard, Alexandre Giulietti, Veerle Derudder, J-W Weijers, Steven Dupont, Lieven Hollevoet, Francky Catthoor, Liesbet Van der Perre, Hugo De Man, Rudy Lauwereins
发表日期
2003/2/13
研讨会论文
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
页码范围
152-484
出版商
IEEE
简介
A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup 2/. Energy-optimized architecture reduces the energy per bit to 8.7nJ and is almost constant over the throughput range.
引用总数
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B Bougard, A Giulietti, V Derudder, JW Weijers… - 2003 IEEE International Solid-State Circuits …, 2003