查看文章

Turbo codes have become an attractive forward error correction scheme for broadband communications, providing near optimal coding gain. However, the limited throughput, the large latency and the significant power consumption of their current implementations make them hardly suitable for future broadband communication systems (up to 1 Gbit/s). We have developed an innovative turbo-decoding architecture that overcomes these major drawbacks. We increased drastically the throughput and decreased the latency by introducing a high level of parallelism. We reduced significantly the power consumption by optimizing the memory architecture and organization. This paper presents the proposed architecture as a generic, scalable and parametrizable entity. Design trade-offs regarding decoding performance, energy consumption and silicon area are extensively explored and summarized in cost versus …