查看文章

Cognitive Radio requires the architecture of radio systems to combine reception and spectrum monitoring functionality efficiently. We propose a flexible digital front end that supports concurrent synchronization and sensing of high-throughput wireless standards. The chip is implemented in 65 nm CMOS technology resulting in a chip area of 6.4 mm ² . Fine grain clock gating allows synchronization at 4 mW and sensing at 7 mW power consumption. Experiments with the chip in combination with a reconfigurable analog front end show that a 1.7 GHz wide frequency band can be scanned based on energy detection in an exceptionally low time window of 10 ms while consuming 13 mW power. Feature detection of DVB-T signals is implemented and measured as well and achieves for a single autocorrelation step a performance target false alarm rate of 10% and detection probability of 90% at an input power level of …