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The prevalent blocks used in digital signal processing hardware are the adder, multiplier and delay elements. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems. In this paper we have introduced a new (i) 8 transistor (8T) full adder (ii) Proposed Shannon based (8T) adder using pass transistor logic which has better power, delay performance than the existing adders. Performance comparison of the proposed 8T adder has been made by comparing its performance with 10T SERF, 10T CLRCL, and the existing 14T full adders. The proposed 8T full adder structure has improved performance characteristics and suitable for Array, Carry Save and Dadda multipliers. Also three versions of 3 tap FIR filter namely Broadcast, Unfolded …