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FIR filters are commonly used digital filters which find its major application in digital signal processing. In conventional FIR filter, the input vector form is delayed by one sample and then multiplied with filter coefficients which are subsequently accumulated by the adders. The drawbacks due to this are high device utilization and high power consumption. In order to compensate these drawbacks, we propose a reconfigurable FIR filter using radix-4 multiplier. The major changes in the proposed system are radix-4 multiplier for multiplication and change in the basic architecture of the FIR filter. In this method, we combine all the input tap values having similar co-efficient values and then multiplying those with the respective co-efficient. The proposed design is simulated and synthesized using Xilinx. The proposed method is compared with the existing FIR filter. From the results, it is observed that our proposed method has …