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In this paper, design, simulation and implementation design of HDLC Controller provides a high performance. This design is then coded in a hardware description language (VHDL). The functioning of the coded design is to simulate on simulation software (eg ModelSim). After proper simulation, the design is synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model the design is mapped to the existing slices of the FPGA and the post-map model simulated. The post-map model does not include the routing delays. After the successful completion of the post-map simulation, the design is then routed and a post-route simulation model with the appropriate routing delays is generated to be simulated on the HDL simulator. After this a programming file is generated to program the FPGA device. The objective of this paper is to run the programmed FPGA at a frequency as high as possible. HDLC Controller MEGACELL is a high performance module for the bit oriented, switched, non-switched packet transmission module. The controller fulfills the specifications according to ITU Q. 921, X. 25 Level 2 recommendation. It supports half duplex and full duplex communication lines, point-to-point and multipoint channels. Furthermore, the Controller is designed to permit synchronous, code transparent data transmission. The control information is always in the same position and specific bit patterns used for control differ …