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HDLC controller megacell is a high performance module for the bit oriented, switched, non-switched packet transmission module. The controller fulfills the specifications according to ITU q. 921, X. 25 level 2 recommendations. It supports half duplex and full duplex communication lines, point-to-point and multipoint channels. Furthermore, the controller is designed to permit synchronous, code transparent data transmission. The control information is always in the same position and specific bit patterns used for control differ dramatically from those representing data that reduces the chances of errors. The data stream and transmission rate is controlled by the network node. In this paper, we have designed, simulated and implemented HDLC controller. This design is coded in a hardware description language (VHDL). The function of coded design is to simulate on simulation software (eg modelsim). After simulation, the design is synthesized and translated into a structural architecture, in terms of the components on the target FPGA device (Spartan 3) and perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model, the design is mapped to the existing slices of the FPGA and the post-map model simulated. The post-map model does not include the routing delays. The objective of this paper is to run the programmed FPGA at frequency ie it Operates up to 155.52 Mbits/s data rates. In this paper, we implemented the various HDLC controllers for 16-bit address, 8 bit data and 16 bit CRC Check, simulation result for final output at the receiver end for 8 …