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Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. If a system uses this feature the designer has to take care, that no signal lines cross the border to other reconfigurable regions. Traditional solutions connecting modules on a dynamic and partial reconfigurable system use TBUF elements for connection and separation of the functional blocks. While automalically placing and routing the design, the routing-tool sometimes uses signal lines which cross the module border. The constraints given by the designer are ignored. To solve this problem we use slices instead of TBUF elements which leads to a benefit by using an automatic modular design flow. This paper gives an overview of the used technique and the complete system on a Xilinx XC2V3000 FPGA.