作者
Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi, Nooshin Dadkhahi
发表日期
2008/2/1
期刊
J. Comput.
卷号
3
期号
2
页码范围
48-54
简介
In this paper a new low power and high performance adder cell using a new design style called “Bridge” is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room temperature; with supply voltage variation from 0.65 v to 1.5 v with 0.05 v steps.
引用总数
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K Navi, O Kavehei, M Rouholamini, A Sahafi… - J. Comput., 2008