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Super-regeneration is re-examined for its simplicity and power efficiency for low-power, short-range communication. A fully integrated super-regenerative receiver in 0.13-mum CMOS is designed to operate in the 2.4 GHz ISM band. A frequency synthesizer scheme tunes the passband. Successive approximation register (SAR) logic driving a current digital-to-analog converter (DAC) calibrates the quench signal to enhance the selectivity of a Q -enhanced filter and the sensitivity of super-regeneration. A single-chip prototype receiver occupies less than 1 mm ² , has a turn-on time of 83.6 mus, a channel spacing of 10 MHz, and a sensitivity of -90 dBm. A data rate of 500 kb/s is achieved with a power consumption of 2.8 mW, corresponding to energy consumption of 5.6 nJ per received bit.