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This work proposes the design of a new low voltage high output impedance CMOS current mirror that offers enhanced output voltage compliance using bulk-driven technique. The input/output characteristics of the proposed current mirror are discussed. Designed circuit is simulated in a proprietary 180 nm CMOS process, using Cadence Spectre and BSIM3v3 models. Simulated results with 0.8 V power supply and 50 uA input current reveal that the proposed implementation requires a minimum input and output voltages of 0.4 V and 0.39 V respectively. It yields an increase of the output impedance compared with that of existing bulk driven current mirrors, thus offering a potential solution to mitigate the effect of ultra-deep submicron CMOS transistors used in sub 1-V current mirrors and current sources. Compared to high output impedance gate driven regulated cascode current mirror (GDRCCM), low voltage high …