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This paper presents a 94 GHz transmitter chipset in 32nm SOI CMOS. The transmitter employs two 2- bit high-speed RFDACs driven in quadrature, 20 dB gain LO drivers and 30 Gbps high-speed digital retimers and deserializers. The transmitter chip is capable of supporting BPSK/PAM4/QPSK modulation schemes, at a saturated output power P _sat of +4 dBm. A maximum data rate of 20 Gbps was achieved when operating in QPSK mode, and 12 Gbps in BPSK and PAM4 modes. The chip occupies 1.4 × 0.8 mm ² , and consumes 110 mW in BPSK/PAM4 modes and 220 mW in QPSK mode, resulting in a state-of-the-art 9 pJ/bit and 11 pJ/bit efficiency, respectively.