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The synchronous design operates at highest frequency that drives a large load because it has to reach many sequential elements throughout the chip. Thus, clock signals have been a great source of power dissipation because of high frequency and load. Clock signals do not perform any computation and mainly used for synchronization. Hence these signals are not carrying any information. So, by using clock gating one can save power by reducing unnecessary clock activities inside the gated module. In this paper, we present a review of some existing techniques available for clock gating. Also a new technique that provides more immunity to the existing problems in available techniques is discussed.