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Residue Number System (RNS) is an alternative number representation of a Binary weighted system to process the data at a higher rate with lower hardware. Modular Multiplication operations are extensively utilized in RNS Processors. To increase the processor's performance, a new configurable signed dual modulo multiplication that uses array architecture is proposed in this work. The multiplier could be used to perform successive modulo multiplications on the same hardware. Mathematical modelling, VLSI architecture and real-time verification are done in this work. Proposed DMMF saves the area by 40%, reduces the power consumption by 37%, and increases the operation speed by 33% compared to the architecture operated separately.