查看文章

In this paper, we propose the VLSI implementation of a wavelet packet transform-based architecture. Moreover, the proposed architecture is compared to the wavelet transform architecture in terms of their signal denoising capabilities, hardware resources used, maximum operating frequency and maximum combination path delay. The Wavelet packet transform architecture is designed and implemented for db2 and db3 wavelet types. For the proposed real-time VLSI implementation, the Xilinx Spartan-6 series FPGA platform is used. Simulation results show that the proposed architecture implementation results in an improved performance for ECG signals taken from the Fantasia Database as well as from the self-recorded database, as compared to the WT wavelet architectures which result in distorted outputs. Moreover, from the synthesis results, it is concluded that the proposed architecture implementation requires …