作者
S Narasimha, B Jagannathan, A Ogino, D Jaeger, B Greene, C Sheraw, K Zhao, B Haran, U Kwon, AKM Mahalingam, B Kannan, B Morganfeld, J Dechene, C Radens, A Tessier, A Hassan, H Narisetty, I Ahsan, M Aminpur, C An, M Aquilino, A Arya, R Augur, N Baliga, R Bhelkar, G Biery, A Blauberg, N Borjemscaia, A Bryant, L Cao, V Chauhan, M Chen, L Cheng, J Choo, C Christiansen, T Chu, B Cohen, R Coleman, D Conklin, S Crown, A da Silva, D Dechene, G Derderian, S Deshpande, G Dilliway, K Donegan, M Eller, Y Fan, Q Fang, A Gassaria, R Gauthier, S Ghosh, G Gifford, T Gordon, M Gribelyuk, G Han, JH Han, K Han, M Hasan, J Higman, J Holt, L Hu, L Huang, C Huang, T Hung, Y Jin, J Johnson, S Johnson, V Joshi, M Joshi, P Justison, S Kalaga, T Kim, W Kim, R Krishnan, B Krishnan, K Anil, M Kumar, J Lee, R Lee, J Lemon, SL Liew, P Lindo, M Lingalugari, M Lipinski, P Liu, J Liu, S Lucarini, W Ma, E Maciejewski, S Madisetti, A Malinowski, J Mehta, C Meng, S Mitra, C Montgomery, H Nayfeh, T Nigam, G Northrop, K Onishi, C Ordonio, M Ozbek, R Pal, S Parihar, O Patterson, E Ramanathan, I Ramirez, R Ranjan, J Sarad, V Sardesai, S Saudari, C Schiller, B Senapati, C Serrau, N Shah, T Shen, H Sheng, J Shepard, Y Shi, MC Silvestre, D Singh, Z Song, J Sporre, P Srinivasan, Z Sun, A Sutton, R Sweeney, K Tabakman, M Tan, X Wang, E Woodard, G Xu, D Xu, T Xuan, Y Yan, J Yang, KB Yeap, M Yu, A Zainuddin, J Zeng, K Zhang, M Zhao, Y Zhong, R Carter, C-H Lin, S Grunow, C Child, M Lagus, R Fox, E Kaste
发表日期
2017/12/2
研讨会论文
2017 IEEE International Electron Devices Meeting (IEDM)
页码范围
29.5. 1-29.5. 4
出版商
IEEE
简介
We present a fully integrated 7nm CMOS platform featuring a 3 rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um 2 . This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform …
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S Narasimha, B Jagannathan, A Ogino, D Jaeger… - 2017 IEEE International Electron Devices Meeting …, 2017