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Increased process variation and reduced operating voltage present two of the main challenges in using sense amplifiers for small geometry bulk CMOS process technology. This fact coupled with the need to increase on-chip memory to reduce traffic on the bus and increase performance creates the need for a robust and reliable sense amplifier - a differentiating factor in memory area, power, and speed. We present a detailed study of the Voltage Latched Sense Amplifier (VLSA) and the Current Latched Sense Amplifier (CLSA) design in 28nm industry standard process technology [1][2]. We present results on how the two sense amplifier behave for the two design topology for low power (LP) process technology optimized for mobile low leakage application and the second one is high performance High Performance (HP) applications. Detailed Spice simulation with statistical models and Monte Carlo simulations is …