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Cryogenic CMOS processors need low latency, high bandwidth access to high-density on-die cache memory to maximize performance. In this work, we experimentally demonstrate, for the first time, pseudo-static random access memory operation of a 1T Capacitorless Floating Body DRAM using 22nm FDSOI transistor, down to 4.8K, suitable for cryogenic cache memory. We demonstrate a 1T Cryo-DRAM that exhibit: (a) record high sensing current and sense margin , (b) pseudo-static retention characteristics (>10 ⁵ sec); (c) high write endurance > 10 ¹⁰ cycles, and (d) non-destructive read cycles > 10 ¹⁶ , suitable for cache application. Benchmarking reveals that 1T Cryo-DRAM outperforms Cryo-SRAM and Cryo-STT-MRAM in memory density by 10x and 50x; in read/write energy by 2.7x/2.4x and 1.3x/1.5x and in read latency by 1.46x and 1.80x respectively for a cache …