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Cryptographic algorithms are widely used for security purposes. These algorithms have been implemented in software as well in hardware. The hardware implementations gain significant importance due to their higher security provision. In this context, a novel hardware architecture to implement scalar multiplication on the standardized NIST curve over GF(2 ^m ) by using polynomial basis is presented. For scalar multiplication, Lopez and Dahab algorithm have been implemented. The novel architecture is modeled in Verilog and synthesized using Xilinx (ISE 14.2) for different FPGA devices. The performance of proposed architecture is explored by realizing throughput/area at the same time. The achieved throughput/area on Virtex 4, Virtex 5, Virtex 6 and Virtex 7 devices are 2.71, 8.51, 11.82 and 10.80.