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Conventional systems with direct-attached DRAM struggle to meet growing memory capacity demands: the number of channels is limited by pin count, and the number of modules per channel is limited by signal integrity issues. Recent buffer-on-board (BOB) designs move some memory controller functionality to a separate buffer chip, which lets them support larger capacities (by adding more DRAM or denser, non-volatile components). Nonetheless, lower-cost, lower-latency, direct-attached DRAM still represents a better price-performance solution for many applications.

Most processors exclusively implement either the direct-attached or the BOB approach. Combining both technologies within one processor has obvious benefits, but current memory-interface requirements complicate this straightforward solution. The standard DRAM interface is DDR, which requires data to be returned at a fixed latency. In contrast …