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Most of the real world signals have analog behavior. In order to convert these analog signals to digital, we need an analog to digital converter (ADC). In the architecture of ADC’s, comparators are the fundamental blocks. The usage of these dynamic comparators are maximized because of demand for low-power, area efficient and high-speed ADC’s. The dynamic comparator performance depends on technology that we used. This paper presents the design and analysis of dynamic comparators. Based on the analysis, designer can obtain a new design to trade-off between speed and power. In this paper, a p-MOS latch is present along with a pre-amplifier. p-MOS transistors were used as inputs in pre-amplifier and latch. The circuit operates by specific clock pattern. At reset phase, the circuit undergoes discharge state. During evaluation phase, after achieving enough pre-amplification gain, the latch is activated. The …