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This paper presents a delay comparison of two different multipliers for unsigned data, one uses a ripple carry and the second one uses a carry-lookahead adder. The 4× 4 Vedic multiplier module using Urdhva Tiryakbhyam Sutra uses four 2× 2 Vedic multiplier modules. Urdhva tiryakbhyam Sutra is most powerful Sutra, giving minimum delay for multiplication of all types of numbers, either small or large. Urdhva Triyagbhyam–Vedic method for multiplication which strikes a difference in the real process of multiplication itself. It causes parallel generation of intermediate products, removes unwanted multiplication steps with zeros and scaled to higher bit levels. The paper’s main focus is on the speed/delay of the multiplication operation on 4-bit multipliers which are modeled using VHDL, A hardware description language. The 4× 4 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 9.1 software. This multiplier is implemented on Spartan 3 FPGA device XC3S50-5pq208. The performance evaluation results in terms of speed and device utilization. The multiplier with a carry-look-ahead adder has shown a less delay over the multiplier with a ripple carry adder. The multiplier with a ripple adder uses time= 17.796 ns, while the multiplier with the carry-look-ahead adder uses time= 17.560 ns.