发明者
Jaewoong Chung, Hanjun Kim, Youfeng Wu
发表日期
2018/9/18
专利局
US
专利号
10078357
专利申请号
14594465
简介
In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.
学术搜索中的文章
J Chung, H Kim, Y Wu - US Patent 10,078,357, 2018
T Ushiki, K Yamada, Y Itagaki - US Patent 6,837,936, 2005