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This paper presents a compact 4∶1 ratio transformer-based balun design in 65-nm CMOS process. The insertion loss is lower than 1.5 dB from 56 GHz to 64 GHz. The balun also serves as a matching network between the output of mixer and chip output terminal. By choosing appropriate inductance ratio and mutual coupling coefficient, the impedance transforms from (52.9+j85.8) Ω to (29.1+j4.7) Ω. Cascade ABCD parameter de-embedding technique is applied to remove the connection parasitic effects in the testing structure.