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This paper presents a high-power high-efficiency PA design method using traditional fundamental-frequency load pull tuners. Harmonic impedance control at the virtual drain is accomplished through the use of tunable pre-matching circuits and full-wave FEM modeling of package parasitics. A 10-mm gate periphery GaN transistor from TriQuint is characterized using the method, and load-pull contours are presented illustrating the dramatic impact of varying 2nd harmonic termination. A 3rd harmonic termination is added to satisfy conditions for class-F ^-1 load pull, resulting in an 8% efficiency improvement over the best-case 2nd harmonic termination. The method is verified by design and measurement of a 36-W class-F ^-1 PA prototype at 2.14GHz with 81% drain efficiency and 14.5 dB gain (78% PAE) in pulsed operation.