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The constraints of retention time (T _Ret ), speed, and power consumption at fixed total length ( ) and minimum bias levels (4) present bottlenecks in the operation of reconfigurable transistor (RFET) as capacitorless (1T) dynamic random access memory (DRAM). A constraint-aware assessment of 1T-DRAM showcases potential for high with sense margin (SM) > and current ratio (CR) > 10 ² at 85°C. Scaled down 1T-DRAM with exhibits a decent T _Ret (∼35 ms) at write (4 ns) and read (5 ns) time with and which highlights prospects for embedded applications. Disturbance due to shared bit and word lines is also discussed.