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The Built in Self Test (BIST) scheme proposed here is a combination of two test pattern generators. One is Low Transition Random Test Pattern Generator (LT-RTPG) and the other is Arithmetic based 3-weighted Random Test pattern Generator (A-3WRTPG). The LT-RTPG aims at detection of easy to detect faults which are prone to pseudo random patterns and reduction of power consumption during BIST activity. The LT-RTPG uses Bit-Swapping Linear Feedback Shift Register (BS-LFSR) for generation of pseudo random sequences. The BS-LFSR focuses on reducing the transitions in generated test pattern and there by reduces the power consumption during BIST activity. The A-3WRTPG aims at detection of pattern resistant faults that are left undetected by LT-RTPG and thereby increases the detection of fault probability. The A-3WRTPG uses flip flops and adders for carrying out arithmetic operations and modified …