作者
Sherif M Saif, Hazem M Abbas, Salwa M Nassar
发表日期
2003/5/25
研讨会论文
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS'03.
卷号
2
页码范围
II-II
出版商
IEEE
简介
This paper presents a Field Programmable Gate Array (FPGA) implementation for video compression using a Block Truncation Coding (BTC) image compression technique. The implementation exploits the inherent parallelism of the BTC algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide 20.5 /spl times/ 10/sup 6/ of pixels per second, which is about 3000 times faster than an Intel Pentium III 550 MHz processor.
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SM Saif, HM Abbas, SM Nassar - Proceedings of the 2003 International Symposium on …, 2003