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The authors present a hardware implementation of the advanced encryption standard (AES) which is optimised for low-resource requirements. The standard-cell implementation on a 0.35 µm CMOS process from Philips Semiconductors occupies an area of only 0.25 mm2. This compares roughly to 3400 gate equivalents or to the size of a small grain of sand. The authors believe that this size will serve for a long time as a reference for AES-128 implementations that support encryption and decryption including key setup. Their manufactured silicon implementation is fully operational. Measurements verified the excellent performance predicted by simulation. The maximum clock frequency of 80 MHz allows a data throughput rate of 9.9 Mbps. Besides low-resource optimisation, the circuit is optimised for low-power operation. For use in low-throughput applications, the AES module draws only a current of 3.0 µA …