| 2, 3-Dichloro-5, 6-dicyanobenzoquinone and its reactions D Walker, JD Hiebert Chemical reviews 67 (2), 153-195, 1967 | 638 | 1967 |
| Yield simulation for integrated circuits DM Walker Springer Science & Business Media, 2013 | 161 | 2013 |
| K longest paths per gate (KLPG) test generation for scan-based sequential circuits W Qiu, J Wang, DMH Walker, D Reddy, X Lu, Z Li, W Shi, H Balachandran 2004 International Conferce on Test, 223-231, 2004 | 152 | 2004 |
| An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit W Qiu, DMH Walker International Test Conference, 2003. Proceedings. ITC 2003., 592-592, 2003 | 148 | 2003 |
| Resistive bridge fault modeling, simulation and test generation VR Sar-Dessai, DMH Walker International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999 | 109 | 1999 |
| Longest-path selection for delay test under process variation X Lu, Z Li, W Qiu, DMH Walker, W Shi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 107 | 2005 |
| Power supply noise in delay testing J Wang, DMH Walker, A Majhi, B Kruseman, G Gronthoud, LE Villagra, ... 2006 IEEE International Test Conference, 1-10, 2006 | 99 | 2006 |
| A circuit level fault model for resistive opens and bridges Z Li, X Lu, W Qiu, W Shi, DMH Walker Proceedings. 21st VLSI Test Symposium, 2003., 379-384, 2003 | 80 | 2003 |
| IDDX-based test methods: A survey SS Sabade, DM Walker ACM Transactions on Design Automation of Electronic Systems (TODAES) 9 (2 …, 2004 | 63 | 2004 |
| Improved wafer-level spatial analysis for I/sub DDQ/limit setting S Sabade, DMH Walker Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 82-91, 2001 | 58 | 2001 |
| Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages Y Liao, DMH Walker Proceedings International Test Conference 1996. Test and Design Validity …, 1996 | 56 | 1996 |
| Test generation for global delay faults GM Luong, DMH Walker Proceedings International Test Conference 1996. Test and Design Validity …, 1996 | 52 | 1996 |
| Evaluation of effectiveness of median of absolute deviations outlier rejection-based I/sub DDQ/testing for burn-in reduction SS Sabade, DM Walker Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 81-86, 2002 | 51 | 2002 |
| Dynamic compaction for high quality delay test Z Wang, DMH Walker 26th IEEE VLSI Test Symposium (vts 2008), 243-248, 2008 | 50 | 2008 |
| FedEx-a fast bridging fault extractor Z Stanojevic, DMH Walker Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 696-703, 2001 | 50 | 2001 |
| Timing analysis of combinational circuits including capacitive coupling and statistical process variation B Choi, DMH Walker Proceedings 18th IEEE VLSI Test Symposium, 49-54, 2000 | 49 | 2000 |
| A vector-based approach for power supply noise analysis in test compaction J Wang, Z Yue, X Lu, W Qiu, W Shi, DMH Walker IEEE International Conference on Test, 2005., 10 pp.-526, 2005 | 48 | 2005 |
| A circuit level fault model for resistive bridges Z Li, X Lu, W Qiu, W Shi, DMH Walker ACM transactions on design automation of electronic systems (TODAES) 8 (4 …, 2003 | 43 | 2003 |
| A fast algorithm for critical path tracing in VLSI digital circuits L Wu, DMH Walker 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 41 | 2005 |
| Static compaction of delay tests considering power supply noise J Wang, W Qiu, S Fancler, DMH Walker, X Lu, Z Yue, W Shi 23rd IEEE VLSI Test Symposium (VTS'05), 235-240, 2005 | 40 | 2005 |
