| Orally Disintegration systems: Innovations in formulation and Technology G Honey, R Parshuram, R Vikas, KT Ashok Recent patents on drug delivery & formulation 2, 258-274, 2008 | 26 | 2008 |
| A 32-KB ePCM for real-time data processing in automotive and smart power applications M Pasotti, R Zurla, M Carissimi, C Auricchio, D Brambilla, E Calvetti, ... IEEE Journal of Solid-State Circuits 53 (7), 2114-2125, 2018 | 20 | 2018 |
| Stress relaxed multiple output high-voltage level shifter V Rana, R Sinha IEEE Transactions on Circuits and Systems II: Express Briefs 65 (2), 176-180, 2017 | 19 | 2017 |
| 2-Mb embedded phase change memory with 16-ns read access time and 5-Mb/s write throughput in 90-nm BCD technology for automotive applications M Carissimi, R Zurla, C Auricchio, E Calvetti, L Capecchi, L Croce, ... ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 17 | 2019 |
| CMOS oscillator having stable frequency with process, temperature, and voltage variation R Vikas US Patent 9,325,323, 2016 | 15 | 2016 |
| A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications M Pasotti, M Carissimi, C Auricchio, D Brambilla, E Calvetti, L Capecchi, ... ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 320-323, 2017 | 10 | 2017 |
| Voltage doubling circuit and charge pump applications for the voltage doubling circuit R Vikas, M Pasotti, F De Santis US Patent 9,634,562, 2017 | 10 | 2017 |
| Single stage cascoded voltage level shifting circuit R Sinha, R Vikas US Patent 9,755,621, 2017 | 9 | 2017 |
| Word line driver for memory R Vikas US Patent 8,750,049, 2014 | 9 | 2014 |
| Circuit for level shifting a clock signal using a voltage multiplier R Vikas US Patent 10,050,524, 2018 | 8 | 2018 |
| Row decoder for non-volatile memory devices and related methods M Pasotti, R Vikas US Patent 9,466,347, 2016 | 7 | 2016 |
| Negative voltage level shifter circuit R Vikas US Patent 8,461,899, 2013 | 7 | 2013 |
| Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation R Vikas US Patent 10,461,636, 2019 | 6 | 2019 |
| Row decoder for embedded Phase Change Memory using low voltage transistors V Rana, M Pasotti, M Carissimi Microelectronics Journal 81, 117-122, 2018 | 5 | 2018 |
| Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation R Vikas US Patent 10,811,960, 2020 | 4 | 2020 |
| Switched capacitor based high positive and negative voltage charge-pump using sample and hold technique V Rana, A Mittal 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 78-81, 2018 | 4 | 2018 |
| Single charge-pump generating high positive and negative voltages driving common load V Rana, M Pasotti, F Desantis 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017 | 4 | 2017 |
| Non-volatile memory with reduced sub-threshold leakage during program and erase operations R Vikas, F De Santis US Patent 9,159,425, 2015 | 4 | 2015 |
| Circuit and method to detect word-line leakage and process defects in non-volatile memory array R Vikas, V Tyagi US Patent 11,935,607, 2024 | 3 | 2024 |
| Positive and negative charge pump control R Vikas, M Pasotti, F De Santis US Patent 11,424,676, 2022 | 3 | 2022 |
Marcella CarissimiSTMicroelectronic在 st.com 的电子邮件经过验证
Marcella CarissimiSTMicroelectronic在 st.com 的电子邮件经过验证